AKTU Computer Organization and Architecture · Important Questions 2026Source: ryzenstudy.com PYQs
BCS302 Computer Organization and Architecture Important Questions 2026 (AKTU)
Repeat analysis + most-asked questions, unit-wise
What we did: built from all 5 AKTU Computer Organization and Architecture papers (2021-22–2025-26): 117 questions grouped into 74 distinct questions, 28 of which were asked in more than one paper.
- of marks were repeat questions
- 57%
- of marks were repeat questions
- questions asked in 2+ papers
- 28
- questions asked in 2+ papers
- papers analysed (2021-22–2025-26)
- 5
- papers analysed (2021-22–2025-26)
- units, mapped to current syllabus
- 5
- units, mapped to current syllabus
How much of the paper repeats?
- Repeats are real: when we checked each newer BCS302 paper against the papers before it, on average 57% of its marks were questions already asked in an earlier paper.
- 2023-24 paper: 48% of marks were repeats (8 of 10 repeated questions were in our top list).
- 2024-25 paper: 46% of marks were repeats (2 of 9 repeated questions were in our top list).
- 2025-26 paper: 76% of marks were repeats (6 of 17 repeated questions were in our top list).
- Topic weightage is a guide, not a guarantee: our Tier 1 + Tier 2 topics covered 59% of the next paper's marks — picking the same number of topics at random would have covered about 53%.
Across 10 subjects and 23 papers we tested, 43% of marks repeated earlier questions on average.
1.Unit-wise most-asked questions
Ranked by how many papers asked them, then by how recently. Click a paper to open it.
Unit 1: Introduction
22% of past marks| Question | Asked |
|---|---|
| Explain the functional units of a digital computer system. | Asked 4× |
| What is a bus? Explain different types of buses used in a computer system. | Asked 3× |
| What is a register? Explain general-purpose and special-purpose registers. | Asked 2× |
| Discuss the process of data transfer between registers, buses, and memory units in a digital system. Include explanations of read and write operations. | Asked 2× |
Unit 2: Arithmetic and logic unit · Multiplication
21% of past marks| Question | Asked |
|---|---|
| Explain signed number multiplication using Booth's Algorithm. Multiply A x B where A = -5 and B = 3 using Booth's Algorithm. | Asked 4× |
| Explain the working of carry look-ahead adder with the help of an example. | Asked 4× |
| Multiply the following numbers using Array Multiplier technique (see original paper) | Asked 2× |
| Explain the design of an Arithmetic and Logic Unit. Describe various arithmetic and logical operations performed by ALU. | Asked 2× |
Unit 3: Control Unit · Hardwire and micro programmed control
20% of past marks| Question | Asked |
|---|---|
| Differentiate between hardwired and micro programmed control unit. Explain each component of hardwired control unit organization. | Asked 3× |
| Explain different types of instructions. Explain various instruction formats with suitable examples. | Asked 2× |
| Explain the concept of RISC architecture. Discuss its features and advantages. Compare RISC with CISC architecture. | Asked 2× |
| What are micro-operations? Explain different types of micro-operations. | Asked 2× |
Unit 4: Memory · Cache memories
20% of past marks| Question | Asked |
|---|---|
| Explain the memory hierarchy with diagram. A memory chip has a capacity of 64K x 8. i. Find the number of address lines required. ii. How many such chips are needed to design a 256K x 16 memory system? | Asked 3× |
| Explain 2D and 2 1/2 D memory organization. Write their advantages and disadvantages. | Asked 2× |
| Discuss the characteristics and functionalities of auxiliary memories such as magnetic disks, magnetic tapes, and optical disks. | Asked 2× |
| Explain the direct mapping technique. Consider a digital computer has a memory unit of 64K x 16 and cache memory of 1K words. The cache uses direct mapping with block size of four words. (i) How many bits are there in the tag, block and word fields of the address format? (ii) How many blocks can the cache accommodate? | Asked 2× |
Unit 5: Input / Output · Modes of Data Transfer · Serial Communication
18% of past marks| Question | Asked |
|---|---|
| Explain the working of Direct Memory Access. Describe the DMA controller and its advantages over other I/O methods. | Asked 3× |
| Explain the concept of interrupts. Describe interrupt hardware and explain different types of interrupts. | Asked 2× |
| What is an I/O interface? Explain its functions. Why is an interface required between CPU and I/O devices? | Asked 2× |
| Define and differentiate synchronous and asynchronous communication with example. | Asked 2× |
2.Topic weightage: which topics carry the marks
Blue = Tier 1 + Tier 2 (topics that carried ~80% of past marks). Grey = the rest. It shows where marks have gone, not a promise of what comes next.
Signed multiplication and Booth · U2
6.5% (cum 7%)
Cache address mapping · U4
4.8% (cum 11%)
Register, bus and memory transfer · U1
4.6% (cum 16%)
I/O interface and ports · U5
4.6% (cum 21%)
Hardwired and microprogrammed control · U3
4.5% (cum 25%)
Direct Memory Access · U5
4.4% (cum 29%)
IEEE floating point standard · U2
4.2% (cum 34%)
Processor and register organization · U1
4.1% (cum 38%)
Stack organization · U1
4% (cum 42%)
Auxiliary memories · U4
3.7% (cum 45%)
Buses and bus architecture · U1
3.7% (cum 49%)
Look-ahead carry adders · U2
3.5% (cum 53%)
Pipelining · U3
3.3% (cum 56%)
Asynchronous data transfer · U5
3.2% (cum 59%)
Memory hierarchy · U4
3% (cum 62%)
Functional units · U1
2.7% (cum 65%)
Horizontal and vertical microprogramming · U3
2.6% (cum 67%)
Array multiplier · U2
2.4% (cum 70%)
Virtual memory · U4
2.4% (cum 72%)
Instruction cycle and sub cycles · U3
2.3% (cum 75%)
Floating point arithmetic · U2
2.2% (cum 77%)
Microprogram sequencing · U3
2.2% (cum 79%)
Interrupts · U5
2.2% (cum 81%)
ALU design · U2
2.2% (cum 83%)
Cache performance and locality · U4
1.9% (cum 85%)
Semiconductor RAM · U4
1.8% (cum 87%)
Instruction types and formats · U3
1.6% (cum 89%)
RISC and CISC · U3
1.6% (cum 90%)
Micro-operations · U3
1.6% (cum 92%)
2D and 2.5D organization · U4
1.5% (cum 93%)
Synchronous and asynchronous communication · U5
1.5% (cum 95%)
Bus arbitration · U1
1.5% (cum 96%)
Programmed and interrupt I/O · U5
1.1% (cum 97%)
Addressing modes · U1
1% (cum 98%)
ROM memories · U4
0.6% (cum 99%)
Peripheral devices · U5
0.6% (cum 100%)
Division and logic operations · U2
0.4% (cum 100%)
| Topic | Papers | Share |
|---|---|---|
| Signed multiplication and Booth · Unit 2 · Tier 1 | 5/5 | 6.5% |
| Cache address mapping · Unit 4 · Tier 1 | 4/5 | 4.8% |
| Register, bus and memory transfer · Unit 1 · Tier 1 | 3/5 | 4.6% |
| I/O interface and ports · Unit 5 · Tier 1 | 3/5 | 4.6% |
| Hardwired and microprogrammed control · Unit 3 · Tier 1 | 4/5 | 4.5% |
| Direct Memory Access · Unit 5 · Tier 1 | 4/5 | 4.4% |
| IEEE floating point standard · Unit 2 · Tier 1 | 4/5 | 4.2% |
| Processor and register organization · Unit 1 · Tier 1 | 4/5 | 4.1% |
| Stack organization · Unit 1 · Tier 1 | 3/5 | 4% |
| Auxiliary memories · Unit 4 · Tier 1 | 4/5 | 3.7% |
| Buses and bus architecture · Unit 1 · Tier 1 | 4/5 | 3.7% |
| Look-ahead carry adders · Unit 2 · Tier 1 | 4/5 | 3.5% |
| Pipelining · Unit 3 · Tier 2 | 3/5 | 3.3% |
| Asynchronous data transfer · Unit 5 · Tier 2 | 2/5 | 3.2% |
| Memory hierarchy · Unit 4 · Tier 2 | 3/5 | 3% |
| Functional units · Unit 1 · Tier 2 | 4/5 | 2.7% |
| Horizontal and vertical microprogramming · Unit 3 · Tier 2 | 2/5 | 2.6% |
| Array multiplier · Unit 2 · Tier 2 | 2/5 | 2.4% |
| Virtual memory · Unit 4 · Tier 2 | 2/5 | 2.4% |
| Instruction cycle and sub cycles · Unit 3 · Tier 2 | 2/5 | 2.3% |
| Floating point arithmetic · Unit 2 · Tier 2 | 2/5 | 2.2% |
| Microprogram sequencing · Unit 3 · Tier 2 | 2/5 | 2.2% |
| Interrupts · Unit 5 · Tier 2 | 2/5 | 2.2% |
| ALU design · Unit 2 · Tier 3 | 3/5 | 2.2% |
| Cache performance and locality · Unit 4 · Tier 3 | 2/5 | 1.9% |
| Semiconductor RAM · Unit 4 · Tier 3 | 3/5 | 1.8% |
| Instruction types and formats · Unit 3 · Tier 3 | 2/5 | 1.6% |
| RISC and CISC · Unit 3 · Tier 3 | 2/5 | 1.6% |
| Micro-operations · Unit 3 · Tier 3 | 2/5 | 1.6% |
| 2D and 2.5D organization · Unit 4 · Tier 3 | 2/5 | 1.5% |
| Synchronous and asynchronous communication · Unit 5 · Tier 3 | 2/5 | 1.5% |
| Bus arbitration · Unit 1 · Tier 3 | 2/5 | 1.5% |
| Programmed and interrupt I/O · Unit 5 · Tier 3 | 1/5 | 1.1% |
| Addressing modes · Unit 1 · Tier 3 | 1/5 | 1% |
| ROM memories · Unit 4 · Tier 3 | 1/5 | 0.6% |
| Peripheral devices · Unit 5 · Tier 3 | 1/5 | 0.6% |
| Division and logic operations · Unit 2 · Tier 3 | 1/5 | 0.4% |
3.Paper pattern (2025-26)
| Section | Questions | Rule |
|---|---|---|
| A | 7 × 2 marks | Attempt all |
| B | 5 × 7 marks | Attempt any 3 |
| C | 10 × 7 marks | Attempt any 1 |
4.In the syllabus, never asked yet
Low priority, but read them once — a new paper can always start here.
- I/O channels and processors · U5
5.Study order
- 1Signed multiplication and Booth (Unit 2, Tier 1)
- 2Cache address mapping (Unit 4, Tier 1)
- 3Register, bus and memory transfer (Unit 1, Tier 1)
- 4I/O interface and ports (Unit 5, Tier 1)
- 5Hardwired and microprogrammed control (Unit 3, Tier 1)
- 6Direct Memory Access (Unit 5, Tier 1)
- 7IEEE floating point standard (Unit 2, Tier 1)
- 8Processor and register organization (Unit 1, Tier 1)
- 9Stack organization (Unit 1, Tier 1)
- 10Auxiliary memories (Unit 4, Tier 1)
- 11Buses and bus architecture (Unit 1, Tier 1)
- 12Look-ahead carry adders (Unit 2, Tier 1)
- 13Pipelining (Unit 3, Tier 2)
- 14Asynchronous data transfer (Unit 5, Tier 2)
- 15Memory hierarchy (Unit 4, Tier 2)
- 16Functional units (Unit 1, Tier 2)
- 17Horizontal and vertical microprogramming (Unit 3, Tier 2)
- 18Array multiplier (Unit 2, Tier 2)
- 19Virtual memory (Unit 4, Tier 2)
- 20Instruction cycle and sub cycles (Unit 3, Tier 2)
- 21Floating point arithmetic (Unit 2, Tier 2)
- 22Microprogram sequencing (Unit 3, Tier 2)
- 23Interrupts (Unit 5, Tier 2)
FAQ
Which units of BCS302 carry the most marks?
Unit 1 (Introduction, 22% of past marks) and Unit 2 (Arithmetic and logic unit · Multiplication, 21% of past marks).
Do AKTU Computer Organization and Architecture questions repeat?
Yes. On average 57% of the marks in each newer BCS302 paper came from questions already asked in an earlier paper, and 28 questions have appeared in more than one paper.
How is this list made?
Every question from the 5 papers (2021-22–2025-26) was mapped to the current AKTU syllabus and grouped with the same question from other years. Questions are ranked by how many papers they appeared in, then by how recently.
Study this subject
Note: this is based on past AKTU papers, not a guarantee. Questions are mapped to the current syllabus; topics that are no longer in the syllabus are left out.