B.TechSemester 52023-24Advance Digital Design Using VerilogKEC054

Advance Digital Design Using Verilog (KEC054) - AKTU Question Paper 2023-24

B.Tech · Semester 5 · Free PDF Download

This is the official AKTU Advance Digital Design Using Verilog Previous Year Question Paper for B.Tech Semester 5, academic session 2023-24. Published by Dr. A.P.J. Abdul Kalam Technical University (AKTU/UPTU), Lucknow. Free PDF download — no login required.

Course:B.Tech

Semester:Semester 5

Session:2023-24

University:AKTU / UPTU

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Questions Asked in 2023-24

Advance Digital Design Using Verilog (KEC054) — complete question paper · 100 marks · 3 Hours

Section AAttempt all q u e s t i o n s i n b r i e f . 2 x 10 = 20

a
What is don’t care handling? 2 1
b
What is meant by combinational logic? 2 1
c
What do you mean by comparator? 2 2
d
What is elimination of hazards? 2 2
e
Give an example of a synchronous circuit 2 3
f
What is Asynchronous Sequential Circuit Design? 2 3
g
Define fault sensitization 2 4
h
What is the use of initial in Verilog code? 2 4 i. What are 4 basic elements of FPGA? 2 5 j. What does PLA stand for? 2 5

Section BAttempt any three o f t h e f o l l o w i n g : 10 x 3 = 30

a
Describe the XOR Pattern handling in digital design. 10 1
b
Describe the techniques and methods used in structural specific ations logic circuits with Verilog
c
Explain the working of ASM charts 10 3
d
Explain the working of BDD in digital design. 10 4
e
Draw and explain the architecture of ASIC 10 5

Section CAttempt any one p a r t o f t h e f o l l o w i n g : 10 x 1 = 10

a
Explain mixed logic in digital design 10 1
b
Explain Logic Representation and Minimization with cost in digital design 10 1
a
Discuss Behavioral and Structural specification of logic circuits 10 2
b
How Boolean function are implementation using Verilog? 10 2
a
Explain Mapping Algorithm 10 3
b
Discuss Multi-level minimization and optimization. 10 3
a
Explain Fault Detection and Analysis in combinational and sequential systems 10 4
b
What is Factoring? Discuss Binary decision diagram. 10 4
a
Explain the design of Combinational circuit using CPLD. 10 5
b
How a sequential circuit can be designed using FPGA? 10 5

Question text is extracted from the official AKTU question paper PDF above. Hindi translations are omitted — every question is printed in English in the original paper. Last verified: 2026-08-23.