B.TechSemester 62024-25CMOS Digital Design TechniquesBEC063
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CMOS Digital Design Techniques (BEC063) - AKTU Question Paper 2024-25

B.Tech · Semester 6 · Free PDF Download

This is the official AKTU CMOS Digital Design Techniques Previous Year Question Paper for B.Tech Semester 6, academic session 2024-25. Published by Dr. A.P.J. Abdul Kalam Technical University (AKTU/UPTU), Lucknow. Free PDF download — no login required.

Course:B.Tech
Semester:Semester 6
Session:2024-25
University:AKTU / UPTU

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Questions Asked in 2024-25

CMOS Digital Design Techniques (BEC063) — extracted question text · 70 marks · 3 Hours

Section AAttempt all q u e s t i o n s i n b r i e f . 0 2 x 7 = 1 4
  • a
    Define wafer preparation and lithography in VLSI fabrication. CO
  • b
    Explain the significance of threshold voltage in a MOSFET. CO
  • c
    Differentiate between enhancement and depletion MOSFETs. CO
  • d
    What is trans conductance in MOSFETs? CO
  • e
    Explain lambda-based design rule in CMOS layout. CO
  • f
    Calculate propagation delay of a CMOS inverter with output cap acitance 10fF and ON resistance 5kΩ
  • g
    What is the function of sense amplifier in SRAM? CO
Section BAttempt any three o f t h e f o l l o w i n g : 0 7 x 3 = 2 1
  • a
    Explain CMOS n-well fabrication process with diagram. CO
  • b
    Derive threshold voltage equation for MOSFET and discuss affecting factors. CO
  • c
    Design CMOS inverter and analyze its voltage transfer characteristics. CO
  • d
    Compare pseudo-NMOS logic and transmission gate logic with circuits. CO
  • e
    Explain working of Schmitt trigger circuit and its applicati ons. CO
Section CAttempt any one p a r t o f t h e f o l l o w i n g : 0 7 x 1 = 0 7
  • a
    Explain second-order effects (DIBL, CLM, Body Effect) in MOSFETs. CO
  • b
    Discuss scaling effects in CMOS technology on power, speed and density. CO
  • a
    Derive noise margin expressions for CMOS inverter and explain significance. CO
  • b
    Design 2-input NAND gate using CMOS and analyze power dissip ation. CO
  • a
    Explain dynamic CMOS logic circuit working with example and advantages. CO
  • b
    Design D-latch using transmission gates and explain operation. CO
  • a
    Explain 6T SRAM cell operation with diagram. Difference from DRAM. CO
  • b
    Discuss ASIC design flow and compare full-custom vs semi-custom approaches. CO
  • a
    Calculate average dynamic power dissipation of CMOS inverter with 20fF load at 100MHz if rise time is 2ns
  • b
    Explain row and column decoder circuit in memory design with diagram. CO

Question text is extracted from the official AKTU question paper PDF above. Check the original PDF for equations, diagrams and complete wording. Extracted: 2026-08-23.

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