MCASemester 12023-24Computer Organization ArchitectureKCA-105

Computer Organization Architecture (KCA-105) - AKTU Question Paper 2023-24

MCA · Semester 1 · Free PDF Download

This is the official AKTU Computer Organization Architecture Previous Year Question Paper for MCA Semester 1, academic session 2023-24. Published by Dr. A.P.J. Abdul Kalam Technical University (AKTU/UPTU), Lucknow. Free PDF download — no login required.

Course:MCA

Semester:Semester 1

Session:2023-24

University:AKTU / UPTU

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Questions Asked in 2023-24

Computer Organization Architecture (KCA-105) — complete question paper · 100 marks · 3 Hours

Section AAttempt all q u e s t i o n s i n b r i e f . 2 x 10 = 20

a
Let M = 11111010 and N = 00001010 be two 8-bit two’s complimen t number. Their product in two’s complement is --------------. 2 1
b
Differentiate between clock c ycles and clock frequency. 2 1
c
Explain the role of program counter. 2 2
d
A bulb in a staircase has two switches, one switch being on th e ground floor and the other one on the first floor. The bulb can be turned ON and also can be turned OFF by any one of the switches, irrespective of the state of the other switch. The logic of switching of the bulb resembles to which gate
e
Describe any four status bits i n detail by taking suitable example. 2 3
f
Discuss the concept of PSW. 2 3
g
Differentiate between write ba ck and write through in cache memory. 2 4
h
Differentiate between SRAM and DRAM. 2 4 i. Explain maskable and non-maskable interrupt. 2 5 j. Distinguish between burst transfe r and cycle stealing method. 2 5

Section BAttempt any three o f t h e f o l l o w i n g :

a
Explain the function of control unit in general register org anization with the help of diagram. 10 1
b
Describe BOOTH multiplication algorithm and Multiply (-13) x (-21) and draw the flowchart of Booth’s algorithm. 10 2
c
Show the block diagram of microprogram sequencer. Consider a microprogrammed CU, where 1024-word control memory is used. The CU has to support 40 control signals and 32 flag conditions. How m any bits are required in the control word? What is the size of horizontal and vertical control memory
d
A block-set associative cach e memory consists of 128 blocks divided into four block sets. The main memory consists of 16,384 blocks and each block contains 256 eight-bit words
1
How many bits are required for addressing the main memory?
2
How many bits are needed to represent the TAG, SET and WORD fields?
e
Outline the block diagram of DMA controller. Illustrate, why are the read and write control lines in a DMA controller bidirectional? 10 5

Section CAttempt any one p a r t o f t h e f o l l o w i n g :

a
Illustrate a BUS system? Implement a BUS of 4 lines with MUX. 10 1
b
Demonstrate the concept of add ressing modes. The instruction is stored at location 700 with its address fields at location 701. The addre ss field has the value 1000. A processor re gister contains the value 500 and index re gister contains the value 300. Evaluate the effective address if the addressing mode of the instruction is
a
Direct (b) Indirect (c) Immediate (d) Relative (e) Register Indirect (f) Autoincrement (
a
Explain the concept of 4-bit fast adder in detail along with neat & clean diagram. 10 2
b
Perform the division process of 00001111 by 0011 using divis ion restore method. 10 2
a
Determine a program to evalua te the arithmetic statement.  Using general register computer with 3-address instruction.  Using general register computer with 2-address instruction.  Using an accumulator type computer with 1-address instruction.  Using a stack organized computer with 0-address instruction
b
Compare horizontal microprogramming and vertical microprogramming. The microprogrammed control unit has a control memory of 1024 words of 32 bits each. The micro construction has three fields, and the micro-op erations field has 16 bits
a
How many bits are there in the branch address field and the select field?
b
If there are 16 status bits in the system, how many bits of the branch logic are used to select a status bit?
c
How many bits are left to select an input for the multiplexers
a
Examine the following organizations of cache memory: (i). Associative mapping (ii). Direct Mapping (iii). Set associative mapping. Consider memory block request: 3, 4, 8, 3, 9, 6, 16, 13, 35, 12, 3, 8, 6, 7, 30, 45, 12, 67, 22. Consider a full associative mapping for the 8 cache blocks find the following values for LRU and FIFO  Number of miss and Number of hits  Hit ratio.  Cache block number which contains main memory block 6
b
A processor has 40 distinct in structions and 24 general purp ose registers. A 32-bit instruction word has an opcode, two register operands and an immediate operand. Then find the number of bits available for the immedia te operand field
a
Describe asynchronous data transfer? What are the methods th rough which it can be achieved? 10 5
b
Discuss the modes of trans fer & explain the following. (i) Programmed I/O (ii) Interrupt initiated I/O

Question text is extracted from the official AKTU question paper PDF above. Hindi translations are omitted — every question is printed in English in the original paper. Last verified: 2026-08-23.

Repeated Questions — KCA-105

Questions that appeared in more than one session, found by comparing 4 years of Computer Organization Architecture papers (2021-22, 2022-23, 2023-24, 2024-25)

Outline the block diagram of DMA controller. Illustrate, why are the read and write control lines in a DMA controller bidirectional? 10 5

Appeared in: 2021-22 · 2023-24

Perform the division process of 00001111 by 0011 using divis ion restore method. 10 2

Appeared in: 2021-22 · 2023-24

Computer Organization Architecture — Other Year Papers

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