AKTU Digital Electronics · Important Questions 2026Source: ryzenstudy.com PYQs
BOE310 Digital Electronics Important Questions 2026 (AKTU)
Repeat analysis + most-asked questions, unit-wise
What we did: built from all 8 AKTU Digital Electronics papers (2021-22 (Sem 3)–2025-26 (Sem 4)): 183 questions grouped into 116 distinct questions, 41 of which were asked in more than one paper.
- of marks were repeat questions
- 47%
- of marks were repeat questions
- questions asked in 2+ papers
- 41
- questions asked in 2+ papers
- papers analysed (2021-22 (Sem 3)–2025-26 (Sem 4))
- 8
- papers analysed (2021-22 (Sem 3)–2025-26 (Sem 4))
- units, mapped to current syllabus
- 5
- units, mapped to current syllabus
How much of the paper repeats?
- Repeats are real: when we checked each newer BOE310 paper against the papers before it, on average 47% of its marks were questions already asked in an earlier paper.
- 2022-23 (Sem 3) paper: 27% of marks were repeats (6 of 7 repeated questions were in our top list).
- 2022-23 (Sem 4) paper: 27% of marks were repeats (2 of 6 repeated questions were in our top list).
- 2024-25 (Sem 3) paper: 39% of marks were repeats (2 of 8 repeated questions were in our top list).
- 2024-25 (Sem 4) paper: 58% of marks were repeats (4 of 13 repeated questions were in our top list).
- 2025-26 (Sem 3) paper: 60% of marks were repeats (7 of 13 repeated questions were in our top list).
- 2025-26 (Sem 4) paper: 70% of marks were repeats (7 of 16 repeated questions were in our top list).
- Topic weightage is a guide, not a guarantee: our Tier 1 + Tier 2 topics covered 65% of the next paper's marks — picking the same number of topics at random would have covered about 56%.
Across 10 subjects and 23 papers we tested, 43% of marks repeated earlier questions on average.
1.Unit-wise most-asked questions
Ranked by how many papers asked them, then by how recently. Click a paper to open it.
Unit 1: Digital System and Binary Numbers
21% of past marks| Question | Asked |
|---|---|
| Determine the value of x in the expression, If (56.1A)₁₆ = (x)₈ | Asked 5× |
| Simplify the following Boolean function using K-map and also draw the simplified logic circuit using basic logic gates. (see original paper) | Asked 3× |
| Minimize the following using Quine-Mc Cluskey Method (see original paper) | Asked 3× |
| What is Gray Code? Convert (10010)₂ to Gray Code and explain its significance | Asked 3× |
Unit 2: Combinational Logic
18% of past marks| Question | Asked |
|---|---|
| Explain the design and working of a 2-bit magnitude comparator | Asked 4× |
| Design a Full Adder using two Half Adders and basic gates | Asked 3× |
| Design a 4:1 multiplexer using basic logic gates | Asked 2× |
| Differentiate between the serial and parallel adder | Asked 2× |
Unit 3: Sequential Logic and Its Applications
20% of past marks| Question | Asked |
|---|---|
| Define bi-directional shift register. Draw and explain 3 bit bi-directional shift register using D flip-flop | Asked 3× |
| What is difference between combinational and sequential circuits | Asked 3× |
| Obtain the excitation table of a JK flip flop | Asked 2× |
| Discuss the Race around condition of JK flip flop. How JK flip-flop can be used as T flip-flop, Explain the design procedure | Asked 2× |
Unit 4: Synchronous and Asynchronous Sequential Circuits
21% of past marks| Question | Asked |
|---|---|
| Discuss hazards in asynchronous circuits. How can race conditions be avoided? | Asked 4× |
| Design a sequential circuit with two flip flops A & B and one input x. when x = 0, the state of the circuit remains the same and when x = 1 the circuit passes through the state transitions from 00 to 01 to 11 to 10 back to 00 and repeat | Asked 3× |
| Design a primitive state diagram and state table for a circuit with two asynchronous inputs (X and Y) and one output Z. This circuit is to be designed so that if any change takes place on X and Y, Z is to change states. Assume initially that the two inputs never change simultaneously | Asked 2× |
| Discuss Mealy and Moore FSM. What do you mean by excitation table? | Asked 2× |
Unit 5: Memory and Programmable Logic Devices
20% of past marks| Question | Asked |
|---|---|
| Describe the difference between PAL & PLA using neat diagram and suitable examples | Asked 5× |
| Explain fan-in, fan-out and power dissipation in CMOS logic family | Asked 3× |
| Explain the structure and operation of a static RAM (SRAM) and dynamic RAM (DRAM). | Asked 3× |
| Compare TTL, ECL and CMOS logic families with respect to power dissipation, speed and noise immunity | Asked 2× |
2.Topic weightage: which topics carry the marks
Blue = Tier 1 + Tier 2 (topics that carried ~80% of past marks). Grey = the rest. It shows where marks have gone, not a promise of what comes next.
TTL and ECL families · U5
5% (cum 5%)
Latches and flip flops · U3
4.8% (cum 10%)
State reduction and assignment · U4
4.6% (cum 14%)
RAM and ROM · U5
4.4% (cum 19%)
State machine designing · U4
4% (cum 23%)
Shift registers · U3
4% (cum 27%)
Karnaugh maps up to five variables · U1
3.9% (cum 31%)
PLA and PAL · U5
3.9% (cum 35%)
Number system and arithmetic · U1
3.9% (cum 39%)
NAND and NOR implementation · U1
3.9% (cum 42%)
Asynchronous circuit analysis procedure · U4
3.6% (cum 46%)
Hazards in asynchronous circuits · U4
3.5% (cum 50%)
Multiplexers and demultiplexers · U2
3.4% (cum 53%)
Binary codes and conversion · U1
3.3% (cum 56%)
Flip flop characteristic equations · U3
3.3% (cum 59%)
Synchronous counters · U3
3.1% (cum 63%)
Magnitude comparator · U2
3% (cum 66%)
Subtractors · U2
2.8% (cum 68%)
Half and full adders · U2
2.7% (cum 71%)
Quine McClusky method · U1
2.6% (cum 74%)
Serial and parallel adders · U2
2.3% (cum 76%)
Johnson and ring counters · U3
2% (cum 78%)
Decoders and encoders · U2
2% (cum 80%)
Clocked sequential circuit analysis · U4
1.9% (cum 82%)
Race-free state assignment · U4
1.7% (cum 84%)
CMOS logic family · U5
1.6% (cum 85%)
Design procedure · U4
1.5% (cum 87%)
Flip flop conversion · U3
1.4% (cum 88%)
SOP and POS forms · U1
1.4% (cum 90%)
Noise margin · U5
1.3% (cum 91%)
BCD adder · U2
1.3% (cum 92%)
Implementation using ROM, PLA, PAL · U5
1.3% (cum 93%)
Ripple counters · U3
1.2% (cum 95%)
Signed binary numbers · U1
1.2% (cum 96%)
Fan out and fan in · U5
1.2% (cum 97%)
Interfacing of logic families · U5
0.8% (cum 98%)
Multiplexed display · U2
0.8% (cum 99%)
Boolean algebra and DeMorgan's theorem · U1
0.6% (cum 99%)
DTL and DCTL families · U5
0.5% (cum 100%)
| Topic | Papers | Share |
|---|---|---|
| TTL and ECL families · Unit 5 · Tier 1 | 7/8 | 5% |
| Latches and flip flops · Unit 3 · Tier 1 | 7/8 | 4.8% |
| State reduction and assignment · Unit 4 · Tier 1 | 8/8 | 4.6% |
| RAM and ROM · Unit 5 · Tier 1 | 5/8 | 4.4% |
| State machine designing · Unit 4 · Tier 1 | 4/8 | 4% |
| Shift registers · Unit 3 · Tier 1 | 6/8 | 4% |
| Karnaugh maps up to five variables · Unit 1 · Tier 1 | 6/8 | 3.9% |
| PLA and PAL · Unit 5 · Tier 1 | 7/8 | 3.9% |
| Number system and arithmetic · Unit 1 · Tier 1 | 6/8 | 3.9% |
| NAND and NOR implementation · Unit 1 · Tier 1 | 5/8 | 3.9% |
| Asynchronous circuit analysis procedure · Unit 4 · Tier 1 | 6/8 | 3.6% |
| Hazards in asynchronous circuits · Unit 4 · Tier 1 | 7/8 | 3.5% |
| Multiplexers and demultiplexers · Unit 2 · Tier 1 | 6/8 | 3.4% |
| Binary codes and conversion · Unit 1 · Tier 2 | 7/8 | 3.3% |
| Flip flop characteristic equations · Unit 3 · Tier 2 | 4/8 | 3.3% |
| Synchronous counters · Unit 3 · Tier 2 | 4/8 | 3.1% |
| Magnitude comparator · Unit 2 · Tier 2 | 5/8 | 3% |
| Subtractors · Unit 2 · Tier 2 | 4/8 | 2.8% |
| Half and full adders · Unit 2 · Tier 2 | 4/8 | 2.7% |
| Quine McClusky method · Unit 1 · Tier 2 | 4/8 | 2.6% |
| Serial and parallel adders · Unit 2 · Tier 2 | 4/8 | 2.3% |
| Johnson and ring counters · Unit 3 · Tier 2 | 2/8 | 2% |
| Decoders and encoders · Unit 2 · Tier 2 | 3/8 | 2% |
| Clocked sequential circuit analysis · Unit 4 · Tier 3 | 4/8 | 1.9% |
| Race-free state assignment · Unit 4 · Tier 3 | 3/8 | 1.7% |
| CMOS logic family · Unit 5 · Tier 3 | 3/8 | 1.6% |
| Design procedure · Unit 4 · Tier 3 | 2/8 | 1.5% |
| Flip flop conversion · Unit 3 · Tier 3 | 2/8 | 1.4% |
| SOP and POS forms · Unit 1 · Tier 3 | 3/8 | 1.4% |
| Noise margin · Unit 5 · Tier 3 | 2/8 | 1.3% |
| BCD adder · Unit 2 · Tier 3 | 2/8 | 1.3% |
| Implementation using ROM, PLA, PAL · Unit 5 · Tier 3 | 2/8 | 1.3% |
| Ripple counters · Unit 3 · Tier 3 | 3/8 | 1.2% |
| Signed binary numbers · Unit 1 · Tier 3 | 4/8 | 1.2% |
| Fan out and fan in · Unit 5 · Tier 3 | 3/8 | 1.2% |
| Interfacing of logic families · Unit 5 · Tier 3 | 1/8 | 0.8% |
| Multiplexed display · Unit 2 · Tier 3 | 1/8 | 0.8% |
| Boolean algebra and DeMorgan's theorem · Unit 1 · Tier 3 | 1/8 | 0.6% |
| DTL and DCTL families · Unit 5 · Tier 3 | 2/8 | 0.5% |
3.Paper pattern (2025-26 (Sem 4))
| Section | Questions | Rule |
|---|---|---|
| A | 7 × 2 marks | Attempt all |
| B | 5 × 7 marks | Attempt any 3 |
| C | 10 × 7 marks | Attempt any 1 |
4.In the syllabus, never asked yet
Low priority, but read them once — a new paper can always start here.
- Canonical forms · U1
- Don't care conditions · U1
- Circuits with latches · U4
- Reduction of state and flow table · U4
5.Study order
- 1TTL and ECL families (Unit 5, Tier 1)
- 2Latches and flip flops (Unit 3, Tier 1)
- 3State reduction and assignment (Unit 4, Tier 1)
- 4RAM and ROM (Unit 5, Tier 1)
- 5State machine designing (Unit 4, Tier 1)
- 6Shift registers (Unit 3, Tier 1)
- 7Karnaugh maps up to five variables (Unit 1, Tier 1)
- 8PLA and PAL (Unit 5, Tier 1)
- 9Number system and arithmetic (Unit 1, Tier 1)
- 10NAND and NOR implementation (Unit 1, Tier 1)
- 11Asynchronous circuit analysis procedure (Unit 4, Tier 1)
- 12Hazards in asynchronous circuits (Unit 4, Tier 1)
- 13Multiplexers and demultiplexers (Unit 2, Tier 1)
- 14Binary codes and conversion (Unit 1, Tier 2)
- 15Flip flop characteristic equations (Unit 3, Tier 2)
- 16Synchronous counters (Unit 3, Tier 2)
- 17Magnitude comparator (Unit 2, Tier 2)
- 18Subtractors (Unit 2, Tier 2)
- 19Half and full adders (Unit 2, Tier 2)
- 20Quine McClusky method (Unit 1, Tier 2)
- 21Serial and parallel adders (Unit 2, Tier 2)
- 22Johnson and ring counters (Unit 3, Tier 2)
- 23Decoders and encoders (Unit 2, Tier 2)
FAQ
Which units of BOE310 carry the most marks?
Unit 1 (Digital System and Binary Numbers, 21% of past marks) and Unit 4 (Synchronous and Asynchronous Sequential Circuits, 21% of past marks).
Do AKTU Digital Electronics questions repeat?
Yes. On average 47% of the marks in each newer BOE310 paper came from questions already asked in an earlier paper, and 41 questions have appeared in more than one paper.
How is this list made?
Every question from the 8 papers (2021-22 (Sem 3)–2025-26 (Sem 4)) was mapped to the current AKTU syllabus and grouped with the same question from other years. Questions are ranked by how many papers they appeared in, then by how recently.
Study this subject
Note: this is based on past AKTU papers, not a guarantee. Questions are mapped to the current syllabus; topics that are no longer in the syllabus are left out.