B.TechSemester 32021-22Digital ElectronicsKOE-039

Digital Electronics (KOE-039) - AKTU Question Paper 2021-22

B.Tech · Semester 3 · Free PDF Download

This is the official AKTU Digital Electronics Previous Year Question Paper for B.Tech Semester 3, academic session 2021-22. Published by Dr. A.P.J. Abdul Kalam Technical University (AKTU/UPTU), Lucknow. Free PDF download — no login required.

Course:B.Tech
Semester:Semester 3
Session:2021-22
University:AKTU / UPTU

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Questions Asked in 2021-22

Digital Electronics (KOE-039) — complete question paper

Section AAttempt All of the following Questions in brief Marks(10X2=20) CO
  • a
    How are binary digits used to express the integer and fractional parts of a number? 1
  • b
    Explain how BCD addition is carried out. 1
  • c
    Implement a 4:1 multiplexer using 2:1 multiplexer. 2
  • d
    Demultiplexer is decoder circuit with an additional enabling in put. Do you agree with the above statement?
  • e
    Give the difference between positive and negative edge triggering. 3
  • f
    A flip-flop has 5 ns delay from the time the clock edge occurs to the time the output is complemented. What is the maximum delay in a 10- bit binary ripple counter that uses these flip-flops? What is the maximum frequency the counte r can operate reliably?
  • g
    Define critical race and non-critical race. 4
  • h
    What is the significance of state assignment? 4 Q1(i) Why is ECL logic faster than TTL? 5 Q1(j) Compare static RAM and dynamic RAM. 5
Section BAttempt ANY THREE of the following Questions Marks(3X10=30) CO
  • a
    Realize a 3-input gate using 2-input gates for the following gates: (i) AND (ii) OR (iii) NAND (iv) NOR
  • b
    (i)Implement a full subtractor circuit using only NAND gates. (ii)Using 4:1 multiplexers, implement the following function
  • c
    Define bi-directional shift regi ster. Draw and explain 3 bit bi -directional shift register using D flip-flop
  • d
    Design a primitive state diagram and state table for a circuit with two asynchronous inputs (X and Y) and one output Z. This circuit is to be design ed so that if any change takes place on X and Y, Z is to change states. Assume in itially that the two inputs never change simultaneously
  • e
    (i) Write a note on interfacing TTL with CMOS. (ii) Explain the parameters used to characterize logic families
Section CAttempt ANY ONE following Question Marks (1X10=10) CO
  • a
    Minimize the following using Tabular method
  • b
    (i) Reduce the expression f = ∑ m (0,1,2,3,5,7,8,9,10,12,13) using K-maps an d implement the real minimal expression using NAND logic. (ii) Design the logic circuit for a BCD to decimal decoder
Section CAttempt ANY ONE following Question Marks (1X10=10) CO
  • a
    Construct BCD adder using two 4-bit binary parallel adder and logic gates. 2
  • b
    Explain 4-bit magnitude comparator. 2
Section CAttempt ANY ONE following Question Marks (1X10=10) CO
  • a
    A sequential circuit has one flip-flop Q, two inputs x and y, a nd one output S. It consists of a full-adder circuit connected to a D flip-flop, as shown in given figure. Derive the state table and state diagram of the sequential circ uit. What does this circuit represent?
  • b
    Design a 3-bit UP/DOWN counter with a direction control M, using JK flip-flops. 3
Section CAttempt ANY ONE following Question Marks (1X10=10) CO
  • a
    Derive the transition table for the asynchronous sequential cir cuit shown in given figure. Determine the sequence of internal states Y 1Y2 for the following sequence of inputs x1x2: 00,10,11,01,11,10,00
  • b
    (i)Distinguish between static and dynamic hazard. How will you determine hazard in combinational circuits? (ii)Draw the logic diagram of t he product-of-sums expressionY= (x Show that there is a static 0-hazard when x1 and x3 are equal to 0 and x2 goes from 0 to 1. Find a way to remove the hazard by adding one more OR gate
Section CAttempt ANY ONE following Question Marks (1X10=10) CO
  • a
    Design a BCD to Excess-3 code converter and implement it using a suitable PLA. 5
  • b
    Draw a neat diagram of TTL NAND gate and explain its operation. 5

Question text is extracted from the official AKTU question paper PDF above. Hindi translations are omitted — every question is printed in English in the original paper. Last verified: 2026-08-23.

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