B.TechSemester 42022-23Digital ElectronicsKEE-401

Digital Electronics (KEE-401) - AKTU Question Paper 2022-23

B.Tech · Semester 4 · Free PDF Download

This is the official AKTU Digital Electronics Previous Year Question Paper for B.Tech Semester 4, academic session 2022-23. Published by Dr. A.P.J. Abdul Kalam Technical University (AKTU/UPTU), Lucknow. Free PDF download — no login required.

Course:B.Tech
Semester:Semester 4
Session:2022-23
University:AKTU / UPTU

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Questions Asked in 2022-23

Digital Electronics (KEE-401) — complete question paper

Section AAttempt all questionsinbrief. 2 x 10 = 20
  • a
    Explain Duality Principle. Prove that positive logic AND Gate is equivalent to negative logi c OR Gate
  • b
    Explain 2-input EX-NOR Gate and implement it using minimum number of 2- input NOR Gates
  • c
    Explain Half adder circuit and implement it using 2-input NAND Gates
  • d
    Write down the differences between Combinational and Sequential digital circuits
  • e
    Differentiate between Synchronous and Asynchronous sequential circuits
  • f
    Explain in brief:- (i) Astable Multivibrator (ii) Bistable Multivibrator
  • g
    Explain the working of a PISO type shift register briefly
  • h
    What are Static and Dynamic Hazards? (i) What is Noise Margin? (j) What are the advantages of CMOS logic family?
Section BAttempt any three ofthefollowing: 10x3=30
  • a
    Find the Simplified logical expression for Y. Implement a 1:8 De-mux with selection lines A,B,C using 1:2 De-mux. Verify your implementation with the help of Truth Tables
  • c
    What is Race-Around condition in J-K flip-flop? Explain it’s solution Master- Slave J-K Flip -Flop
  • d
    Given the conditions, such that If input A = 0, the circuit oscillates between either one of the two cases. Case1:- 00-01-00-01 and Case2:- 10-1 1-10-11 And If A = 1, it switches inter between two cases. Draw the state transition diagram and implement the same using JK flip -flop and by using basic logic gates
  • e
    Implement a 3-input NOR Gate using CMOS and DTL logic families. Also Explain the working in both cases
Section CAttempt any one part ofthe following: 10x1=10
  • a
    Implement NOT, OR, AND , EX-OR, EX-NOR, NOR (all 2-inputs except NOT Gate) gates using minimum number of 2 -input NAND Gates
  • b
    Convert all possible 4-bit binary codes into Gray Code. Also show the implementation circuit using 2 -input EX -OR Gates only
  • a
    Implement a circuit using logic gates that compares the magnitudes of two 4- bit numbers
  • b
    Implement the Boolean function F(A,B,C,D)= ∑m(0,1,2,5,8,13,14) using 8:1 MUX with A,C,D as selection lines
  • a
    Implement S-R, T, D flip-flops using J-K flip-flop. Also show the implementation with help of State Tables
  • b
    Design a MOD-12 asynchronous down counter using T flip-flops
  • a
    Given a sequential logic circuit expression as X(t+ 1) = p’X + pY Y(t+1) = pX’+p’Y where X and Y are the two flip-flop outputs and pis the main external input. Draw the state transition table for the above- given logic f unction. Also, draw the state transition diagramassociated with it. Design a synchronous3-bitFSM (which can be used for counting) using D flip-flops with no external inputs and count sequence as follows:- 0- 1-3-7-4-2-0
  • a
    Explain Propogation delay in logic families. Also explain why TPLH >T PHL
  • b
    Explain ROM and its various types. Implement a 4-T SRAM cell using MOSFETs

Question text is extracted from the official AKTU question paper PDF above. Hindi translations are omitted — every question is printed in English in the original paper. Last verified: 2026-08-23.

Repeated Questions — KEE-401

Questions that appeared in more than one session, found by comparing 2 years of Digital Electronics papers (2021-22, 2022-23)

2x

Write down the differences between Combinational and Sequential digital circuits

Appeared in: 2021-22 · 2022-23

2x

Differentiate between Synchronous and Asynchronous sequential circuits

Appeared in: 2021-22 · 2022-23

2x

Implement the Boolean function F(A,B,C,D)= ∑m(0,1,2,5,8,13,14) using 8:1 MUX with A,C,D as selection lines

Appeared in: 2021-22 · 2022-23