MCASemester 12025-26Computer Organization ArchitectureBMC105

Computer Organization Architecture (BMC105) - AKTU Question Paper 2025-26

MCA · Semester 1 · Free PDF Download

This is the official AKTU Computer Organization Architecture Previous Year Question Paper for MCA Semester 1, academic session 2025-26. Published by Dr. A.P.J. Abdul Kalam Technical University (AKTU/UPTU), Lucknow. Free PDF download — no login required.

Course:MCA

Semester:Semester 1

Session:2025-26

University:AKTU / UPTU

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Questions Asked in 2025-26

Computer Organization Architecture (BMC105) — complete question paper · 70 marks · 3 Hours

Section AAttempt all q u e s t i o n s i n b r i e f . 02 x 7 = 14

a
List the functional units of a digital system
b
What is a bus cycle? Give one example
c
Define Booth’s algorithm in one line
d
What is an instruction format?
e
Define 2D memory organization
f
What is programmed I/O?
g
What is SIMD also Write the full form of SIMD

Section BAttempt any three o f t h e f o l l o w i n g : 07 x 3 = 21

a
Explain signed-operand multip lication. Using Booth’s algorit hm, multiply –13 × +11 and show all steps
b
A memory system contains 128K words and a cache of 1K blocks , each block holding 8 words. For direct mapping, determine: (i) Number of main memory blocks (ii) Word offset bits (iii) Index bits (iv) Tag bits Draw the complete ph ysical address format
c
Explain instruction cycle with neat diagrams. Write micro-op erations for Fetch, Decode, and Execute phases
d
Describe Flynn’s classificati on. Compare SISD, SIMD, MISD, M IMD with suitable examples
e
Explain DMA mechanism. Draw the DMA transfer timing for cycl e stealing, and justify why CPU performance is affected

Section CAttempt any one p a r t o f t h e f o l l o w i n g : 07 x 1 = 07

a
Design the architecture of a 3-bus CPU organization and illu strate how the instruction R1 ← R2 + (M[PC ]) is executed using register tr ansfer notation
b
Explain the following addre ssing modes with examples: (i) Immediate (ii) Direct (iii) Register indirect (iv) Indexe
a
Design a 4-bit Carry Look-Ahead Adder and compute: Show all intermediate steps for carr y generation and sum evaluation
b
Convert the decimal value –19.375 into IEEE-754 single preci sion. Show sign, exponent, mantissa, normalization, and biasing
a
Describe microprogram sequenc ing. Explain how conditional br anching is handled in a microprogrammed control unit using a sequencer diagram
b
Explain pipelining. For a 5-s tage pipeline, show pipeline execution of the instruction sequence: LOAD, ADD, SUB, JUMP Indicate hazards and state one solution
a
Explain 2½-D memory organizatio n w i t h a n e a t d i a g r a m . H o w d oes it improve access time compared to 2D organization?
b
Define virtual memory. Explain page fault, working set, and thrashing with examples
a
Explain interrupt hardware a nd interrupt nesting. Draw the s equence of operations during nested interrupt handling
b
Explain parallel processing. Describe shared-memory MIMD and distributed-memory MIMD architectures with diagrams

Question text is extracted from the official AKTU question paper PDF above. Hindi translations are omitted — every question is printed in English in the original paper. Last verified: 2026-08-23.

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