B.TechSemester 32022-23Digital System DesignKEC-302

Digital System Design (KEC-302) - AKTU Question Paper 2022-23

B.Tech · Semester 3 · Free PDF Download

This is the official AKTU Digital System Design Previous Year Question Paper for B.Tech Semester 3, academic session 2022-23. Published by Dr. A.P.J. Abdul Kalam Technical University (AKTU/UPTU), Lucknow. Free PDF download — no login required.

Course:B.Tech

Semester:Semester 3

Session:2022-23

University:AKTU / UPTU

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Questions Asked in 2022-23

Digital System Design (KEC-302) — complete question paper

Section AAttempt all questions in brief. 2 x 10 = 20

a
Explain Minterm and Ma xterm with example
b
Design and draw State Diagram for a 2 bit up/down counter
c
Convert  10523.454 to an Hexadecimal number
d
Draw a full adder using two half adders
e
What do you mean by race around cond ition in JK Flip Flop?
f
Describe figure of merit & noise immunity of TTL & CMOS ICs
g
What is the basic concept of switched capacitors
h
Explain FAN-IN and FAN-OUT. (i) What are the advantages and dis advantages of flash type ADC (j) What is the difference betw een Multiplexer and Encoder

Section BAttempt any three of the following: 10x3=30

a
What is magnitude comparator? Des ign a Single-bit comparator ci rcuit using logic gates
b
Give the general procedure for converting a multilevel AND-OR d iagram into an all NAND diagram. Implement the following Boolean function with NAND gates only.  7,5,4,3,2,1),,( zyxF
c
With neat diagram explain the operation of R-2R DAC
d
Design a universal shift register that performs HOLD, SHIFT RIG HT, SHIFT LEFT, & LOAD operations
e
Draw and Explain a NAND gate in Totem Pole TTL Configuration

Section CAttempt any one part of the following: 10x1=10

a
Simplify the logic function using K-map
b
Implement the function F = ∑m(0,1,3,4,7,8,9,11,14,15) using 8:1 mux
a
Design a 3 bit up/down ripple counter
b
Draw and explain the dual slope analog to digital convertor
a
Minimize y = ∑m(0,1,2,3,5,6,7,8,14,15) + d(4,11,13) using tabular method
b
Explain a Weighted Resistor digital to analog convertor
a
Explain Decoder with neat diagram. Implement the logic expression Y= Σm(2, 4, 6, 7) using decoder as ROM
b
Design a sequential circuit with two Flip Flops, A & B and one input x. When x=0, the State of the circuit remains the same when x=1 the circuit passes through the state transitions from 00 to 01 to 11 to 10 back to 00 & repeat
a
Draw CMOS inverter circuit and explain its working
b
Define PLD’s. Implement the following function using PLA

Question text is extracted from the official AKTU question paper PDF above. Hindi translations are omitted — every question is printed in English in the original paper. Last verified: 2026-08-23.

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