B.TechSemester 62024-25Cmos Digital Design TechniqueBEC063
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Cmos Digital Design Technique (BEC063) - AKTU Question Paper 2024-25

B.Tech · Semester 6 · Free PDF Download

This is the official AKTU Cmos Digital Design Technique Previous Year Question Paper for B.Tech Semester 6, academic session 2024-25. Published by Dr. A.P.J. Abdul Kalam Technical University (AKTU/UPTU), Lucknow. Free PDF download — no login required.

Course:B.Tech
Semester:Semester 6
Session:2024-25
University:AKTU / UPTU

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Questions Asked in 2024-25

Cmos Digital Design Technique (BEC063) — complete question paper · 70 marks · 3 Hours

Section AAttempt all questions in brief. 02x7=14
  • a
    Define wafer preparation and lithography in VLSI fabrication
  • b
    Explain the significance of threshold voltage ina MOSFET
  • c
    Differentiate between enhancement and depletion MOSFETs
  • d
    What is trans conductance in MOSFETs? Explain lambda-based design rule in CMOS layout
  • f
    Calculate propagation delay of a CMOS inverter withroutput capacitance 10fF and cQ4 K3 ON resistance 5kQ. 8 What is the function of sense amplifier in SRAM?
Section BAttempt any three of the following: 07x3=21
  • a
    Explain CMOS n-well fabricationprocéss with diagram
  • b
    Derive threshold voltage equation-for MOSFET and discuss affecting factors. c- Design CMOS inverter and analyze its voltage transfer characteristics
  • d
    Compare pseudo-NMOS logic and transmission gate logic with circuits
  • e
    Explain working of Schmitt trigger circuit and its applications
Section CAttempt any one part of the following: 07x1=07
  • a
    Explain second-order effects (DIBL, CLM, Body.Effect) in MOSFETs
  • b
    Discuss scaling effects in CMOS technology-on power, speed and density
  • a
    Derive noise margin expression$\for CMOS inverter and explain significance
  • b
    Design 2-input NAND gate using CMOS and analyze power dissipation
  • a
    Explain dynamic CMOS logic circuit working with example and advantages. Design D-latch using transmission gates and explain operation. WITH) Paper id: 251024 Roll No
  • a
    Explain 6T SRAM cell operation with diagram. Difference from DRAM
  • b
    Discuss ASIC design flow and compare full-custom vs semi-custom approaches
  • a
    Calculate average dynamic power dissipation of CMOS inverter with 20fF load at cQ4 K3 100MHz if rise time is 2ns. Explain row and column decoder circuit in memory design with diagram

Question text is extracted from the official AKTU question paper PDF above. Hindi translations are omitted — every question is printed in English in the original paper. Last verified: 2026-08-23.

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