B.TechSemester 72022-23Vlsi DesignKEC072
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Vlsi Design (KEC072) - AKTU Question Paper 2022-23

B.Tech · Semester 7 · Free PDF Download

This is the official AKTU Vlsi Design Previous Year Question Paper for B.Tech Semester 7, academic session 2022-23. Published by Dr. A.P.J. Abdul Kalam Technical University (AKTU/UPTU), Lucknow. Free PDF download — no login required.

Course:B.Tech
Semester:Semester 7
Session:2022-23
University:AKTU / UPTU

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Questions Asked in 2022-23

Vlsi Design (KEC072) — complete question paper

Section AAttempt all questions in brief. 2x10 = 20
  • a
    Define the term critical path
  • b
    State the term sheet resistance
  • c
    Define the term Scaling
  • d
    What is a delay in any circuit?
  • e
    What is a cascade circuit?
  • f
    Differentiate between Combi national and Sequential circuits
  • g
    What is a semiconductor memory?
  • h
    Define the term Low-Power circuit. (i) Define the term defects. (j) What is the term testability?
Section BAttempt any three of the following: 10x3 = 30
  • a
    Explaindifferent design methodologies used in VLSI Design
  • b
    Describelinear delay model used in VLSI Design
  • c
    What is noise in VLSI? Define different noise margins used to analyse and circuit
  • d
    Describe different types ofPower dissipation in VLSI circui ts
  • e
    Explain different faults defined in any VLSI circuits
Section CAttempt any one part of the following: 10x1 = 10
  • a
    Describe MOORE’S Law. Give a detailed evolution of VLSI Cir cuits
  • b
    Explain the Y-Chart VLSI design flow by describing each arm separately
  • a
    Describe the term Logical effort and calculate the logical effort of a CMOS 2- input NOR gate
  • b
    Definedifferent types of Scaling used in VLSI Design
  • a
    With a neat diagram make the layout of a 2-input AND gate using CMOS
  • b
    Describe the working and applications np-CMOS logic
  • a
    Explain the working and applications of a 6-T SRAM cell
  • b
    Describe different types of ROM cells
  • a
    With the use of a block diagram, define the Ad-HoC techniqu e for testing a VLSI Circuit
  • b
    DescribeBuilt-in-Self-Test t echnique for testing a VLSI Circuit

Question text is extracted from the official AKTU question paper PDF above. Hindi translations are omitted — every question is printed in English in the original paper. Last verified: 2026-08-23.

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