Vlsi Design (KEC072) - AKTU Question Paper 2024-25
B.Tech · Semester 7 · Free PDF Download
This is the official AKTU Vlsi Design Previous Year Question Paper for B.Tech Semester 7, academic session 2024-25. Published by Dr. A.P.J. Abdul Kalam Technical University (AKTU/UPTU), Lucknow. Free PDF download — no login required.
Course:B.Tech
Semester:Semester 7
Session:2024-25
University:AKTU / UPTU
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Questions Asked in 2024-25
Vlsi Design (KEC072) — complete question paper · 100 marks · 3 Hours
Section AAttempt all questions in brief. 2 x 1 0 = 2 0
- bExplain the importance of critical path analysis in VLSI design
- cWhat is skin effect?
- dCompare the transient response of a lumped and distributed RC model
- eWhat is charge sharing in dynamic CMOS circuits?
- fExplain the cascading of dynamic gates
- gDifferentiate between DRAM and SRAM
- hList the types of non-volatile memories. 4 K1 i. Explain controllability and observability in testing. 5 K2 j. Define fault in the context of digital circuits
Section BAttempt any three of the following: 10 x 3 = 20
- aIllustrate the VLSI design hierarchy and describe the layers of abstraction with examples
- bAnalyze the effects of resistance, capacitance, and inductance on interconnect performance in the distributed RC model
- cExplain the noise considerations in dynamic CMOS design and the ir impact on performance
- dDefine DRAM and SRAM and describe their basic operation principles
- eExplain ad-hoc technique for testability in a combinational circuit
Section CAttempt any one part of the following: 10 x 1 = 10
- aAnalyze the impact of CMOS propagation delay on circuit perform ance, incorporating the concept of sheet resistance
- bDefine the critical path in VLSI design and explain its significance in timing analysis
- aDerive the RC delay model for a given interconnect circuit and calculate its transient response
- bList and explain the parameters affecting interconnects in VLSI circuits
- aAnalyze the problems associated with single-phase clocking in d ynamic CMOS circuits
- bDescribe the steady-state behavior of dynamic CMOS gate circuits
- aExplain the differences between volatile and non-volatile memories with examples
- bAnalyze the power consumption in CMOS circuits and the impact of voltage scaling on power efficiency
- aDefine common faults in digital circuits and their impact on circuit behavior
- bAnalyze the functional modeling of faults at the logic and register levels
Question text is extracted from the official AKTU question paper PDF above. Hindi translations are omitted — every question is printed in English in the original paper. Last verified: 2026-08-23.
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