B.TechSemester 72025-26Vlsi DesignBEC701
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Vlsi Design (BEC701) - AKTU Question Paper 2025-26

B.Tech · Semester 7 · Free PDF Download

This is the official AKTU Vlsi Design Previous Year Question Paper for B.Tech Semester 7, academic session 2025-26. Published by Dr. A.P.J. Abdul Kalam Technical University (AKTU/UPTU), Lucknow. Free PDF download — no login required.

Course:B.Tech
Semester:Semester 7
Session:2025-26
University:AKTU / UPTU

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Questions Asked in 2025-26

Vlsi Design (BEC701) — complete question paper · 70 marks · 3 Hours

Section AAttempt all q u e s t i o n s i n b r i e f . 02 x 7 = 14
  • a
    Define sheet resistance
  • b
    Explain the propagation delay time in brief
  • c
    What is skin effect in interconnects?
  • d
    What is the transient resp onse of an interconnect?
  • e
    List any two noise issues in dynamic CMOS design
  • f
    Interpret power consump tion in CMOS circuits
  • g
    What is controllability in testability analysis?
Section BAttempt any three o f t h e f o l l o w i n g : 07 x 3 = 21
  • a
    Discuss the different design styles used in VLSI in brief. Explain any one style with its features and applications in detail
  • b
    Illustrate the concept of interc onnection models in VLSI design and describe any two models briefly
  • c
    Explain the NORA CMOS (NP-Domino) logic circuit in detail, and provide a brief account of its advantages and disadvantages
  • d
    What do you mean by semiconductor memory? Explain its purpose in digital systems in detail. 4 K5 Outline a concise note on
  • a
    Linear Feedback Shift Registers and their use in testing
  • b
    Built-In Logic Block Observer and its functions
Section CAttempt any one p a r t o f t h e f o l l o w i n g : 07 x 1 = 07
  • a
    Provide a diagram of the lumped RC model for interconnects and illustrate its operation in detail. 2 K4 Outline concise notes on the concepts of
  • b
    Describe the working of static CMOS logic circuits. Also, compa re static CMOS logic with dynamic CMOS logic
  • a
    Explain the operation of a three-transistor DRAM cell, incorporating the concepts of leakage currents and refresh operation
  • b
    Illustrate the circuit diagram of a 6T SRAM cell and describe its read and write operations in detail
  • a
    Explain Built-in Self-Test (BIST) techniques
  • b
    State the necessity of VLSI chip testing. Explain in detail the types of tests, including functional and manufacturing tests

Question text is extracted from the official AKTU question paper PDF above. Hindi translations are omitted — every question is printed in English in the original paper. Last verified: 2026-08-23.

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