AKTU Digital Electronics · Important Questions 2026Source: ryzenstudy.com PYQs

BEE401 Digital Electronics Important Questions 2026 (AKTU)

Repeat analysis + most-asked questions, unit-wise

What we did: built from all 5 AKTU Digital Electronics papers (2021-22–2025-26): 116 questions grouped into 66 distinct questions, 26 of which were asked in more than one paper.

Last Updated: November 12, 2026

of marks were repeat questions: 50%; of marks were repeat questions
questions asked in 2+ papers: 26; questions asked in 2+ papers
papers analysed (2021-22–2025-26): 5; papers analysed (2021-22–2025-26)
units, mapped to current syllabus: 5; units, mapped to current syllabus

How much of the paper repeats?

Repeats are real: when we checked each newer BEE401 paper against the papers before it, on average 50% of its marks were questions already asked in an earlier paper.
2023-24 paper: 43% of marks were repeats (7 of 10 repeated questions were in our top list).
2024-25 paper: 53% of marks were repeats (7 of 12 repeated questions were in our top list).
2025-26 paper: 53% of marks were repeats (7 of 11 repeated questions were in our top list).
Topic weightage is a guide, not a guarantee: our Tier 1 + Tier 2 topics covered 57% of the next paper's marks — picking the same number of topics at random would have covered about 49%.

Across 10 subjects and 23 papers we tested, 43% of marks repeated earlier questions on average.

1.Unit-wise most-asked questions

Ranked by how many papers asked them, then by how recently. Click a paper to open it.

Unit 1:

25% of past marks

Question	Asked
Simplify the Boolean expression using K-map and implement using NAND gates only (expression not readable, see original paper). 7 marks2021-22 Q2(a)2022-23 Q2(a)2023-24 Q2(a)2023-24 Q3(b)2024-25 Q2(a)2025-26 Q2(a)	Asked 5×
Examine the relationship between binary inputs and Gray code outputs in a 4-bit binary to Gray code converter. 7 marks2021-22 Q4(b)2022-23 Q3(b)2025-26 Q4(b)	Asked 3×
Convert the octal number 245 into its decimal equivalent. 2 marks2021-22 Q1(a)2023-24 Q1(a)2025-26 Q1(a)	Asked 3×
Implement the Boolean expression using only NAND gates (expression not readable, see original paper). 7 marks2021-22 Q3(b)2022-23 Q1(b)2022-23 Q3(a)2024-25 Q3(b)	Asked 3×

Unit 2:

17% of past marks

Question	Asked
Implement the logic function given below using a 74151 eight-input data selector/MUX (function not readable, see original paper). 7 marks2021-22 Q2(b)2022-23 Q4(b)2023-24 Q4(b)2024-25 Q4(b)2025-26 Q4(a)	Asked 5×
Implement a 4:1 multiplexer using 2:1 multiplexers. 2 marks2023-24 Q2(b)2024-25 Q1(c)	Asked 2×
What is meant by a half adder? 2 marks2022-23 Q1(c)2023-24 Q1(d)	Asked 2×
Write down the differences between combinational and sequential digital circuits. 2 marks2021-22 Q1(d)2022-23 Q1(d)	Asked 2×

Unit 3: Sequential logic design

25% of past marks

Question	Asked
Examine the state diagram and excitation table of a synchronous decade counter implemented using Toggle flip-flops. 7 marks2021-22 Q2(c)2024-25 Q5(a)2025-26 Q5(a)	Asked 3×
Elucidate the race-around condition in a sequential circuit. 2 marks2021-22 Q5(a)2022-23 Q2(c)2024-25 Q1(d)	Asked 3×
Explain the working of a JK flip-flop with truth table. Also draw its state diagram. 7 marks2023-24 Q2(c)2025-26 Q2(c)	Asked 2×
Discuss the R-S flip-flop in detail. 2 marks2021-22 Q5(b)2024-25 Q1(e)	Asked 2×

Unit 4:

24% of past marks

Question	Asked
Determine the most suitable logic family for a system requirement using given parameters such as power, speed and noise immunity. 7 marks2021-22 Q1(i)2023-24 Q6(a)2024-25 Q2(d)2025-26 Q2(d)	Asked 4×
Describe the architecture and working of a Programmable Logic Array (PLA). 7 marks2021-22 Q7(a)2024-25 Q6(b)2025-26 Q7(b)	Asked 3×
Implement a 3-input NOR gate using CMOS and DTL logic families. Also explain the working in both cases. 7 marks2022-23 Q2(e)2023-24 Q2(e)	Asked 2×
With the help of neat diagrams explain the working of: (i) CMOS NAND gate (ii) CMOS NOR gate. 7 marks2021-22 Q7(b)2023-24 Q6(b)	Asked 2×

Unit 5: ADC Types

10% of past marks

Question	Asked
Explain flash type ADC with a relevant diagram. Discuss its applications. 7 marks2024-25 Q1(g)2025-26 Q7(a)	Asked 2×
Explain the working of dual slope ADC with a neat diagram. 7 marks2023-24 Q7(b)2024-25 Q2(e)	Asked 2×
What do you mean by an R-2R ladder DAC? Explain the working operation of the R-2R ladder DAC. 7 marks2023-24 Q7(a)2024-25 Q7(a)	Asked 2×
A 4-bit R-2R ladder type D/A converter having resistor values R = 10 kΩ and 2R = 20 kΩ uses VR of 10 V. Calculate (a) the resolution of the D/A converter and (b) I0 for a digital input of 1101. 7 marks2025-26 Q2(e)	Asked 1×

2.Topic weightage: which topics carry the marks

Blue = Tier 1 + Tier 2 (topics that carried ~80% of past marks). Grey = the rest. It shows where marks have gone, not a promise of what comes next.

Flip-flops (SR, JK, D, T) · U3

9.3% (cum 9%)

K-map & tabulation method · U1

8.5% (cum 18%)

Multiplexers · U2

7.6% (cum 25%)

CMOS logic family · U4

5.9% (cum 31%)

Adders & subtractors · U2

5.8% (cum 37%)

Clocked sequential circuits · U3

5.2% (cum 42%)

Binary codes & conversion · U1

5.1% (cum 47%)

Boolean algebra & logic gates · U1

5.1% (cum 53%)

Counters · U3

4.2% (cum 57%)

Memories (RAM, ROM) · U4

4% (cum 61%)

Logic family comparison · U4

4% (cum 65%)

PLA, PAL & FPGA · U4

3.5% (cum 68%)

R-2R ladder DAC · U5

3.2% (cum 71%)

Shift registers · U3

3.2% (cum 75%)

SOP, POS & canonical forms · U1

3% (cum 78%)

Number systems & arithmetic · U1

2.8% (cum 80%)

Logic family specifications · U4

2.7% (cum 83%)

Dual slope & counting ADC · U5

2.2% (cum 85%)

TTL logic family · U4

2.2% (cum 88%)

Mealy & Moore machines · U3

2% (cum 90%)

ECL & other families · U4

1.6% (cum 91%)

Combinational circuit design · U2

1.6% (cum 93%)

Flash ADC · U5

1.6% (cum 94%)

Comparators & encoders · U2

1.1% (cum 95%)

Flip-flop conversion · U3

1.1% (cum 96%)

Successive approximation ADC · U5

1% (cum 97%)

Demultiplexers & decoders · U2

1% (cum 98%)

Weighted resistor DAC · U5

1% (cum 99%)

DAC specifications & errors · U5

0.6% (cum 100%)

Topic	Papers	Share
Flip-flops (SR, JK, D, T) · Unit 3 · Tier 1	5/5	9.3%
K-map & tabulation method · Unit 1 · Tier 1	5/5	8.5%
Multiplexers · Unit 2 · Tier 1	5/5	7.6%
CMOS logic family · Unit 4 · Tier 1	3/5	5.9%
Adders & subtractors · Unit 2 · Tier 1	5/5	5.8%
Clocked sequential circuits · Unit 3 · Tier 1	3/5	5.2%
Binary codes & conversion · Unit 1 · Tier 1	4/5	5.1%
Boolean algebra & logic gates · Unit 1 · Tier 1	5/5	5.1%
Counters · Unit 3 · Tier 2	4/5	4.2%
Memories (RAM, ROM) · Unit 4 · Tier 2	3/5	4%
Logic family comparison · Unit 4 · Tier 2	4/5	4%
PLA, PAL & FPGA · Unit 4 · Tier 2	3/5	3.5%
R-2R ladder DAC · Unit 5 · Tier 2	3/5	3.2%
Shift registers · Unit 3 · Tier 2	4/5	3.2%
SOP, POS & canonical forms · Unit 1 · Tier 2	2/5	3%
Number systems & arithmetic · Unit 1 · Tier 2	4/5	2.8%
Logic family specifications · Unit 4 · Tier 3	3/5	2.7%
Dual slope & counting ADC · Unit 5 · Tier 3	2/5	2.2%
TTL logic family · Unit 4 · Tier 3	2/5	2.2%
Mealy & Moore machines · Unit 3 · Tier 3	2/5	2%
ECL & other families · Unit 4 · Tier 3	2/5	1.6%
Combinational circuit design · Unit 2 · Tier 3	3/5	1.6%
Flash ADC · Unit 5 · Tier 3	2/5	1.6%
Comparators & encoders · Unit 2 · Tier 3	1/5	1.1%
Flip-flop conversion · Unit 3 · Tier 3	1/5	1.1%
Successive approximation ADC · Unit 5 · Tier 3	1/5	1%
Demultiplexers & decoders · Unit 2 · Tier 3	1/5	1%
Weighted resistor DAC · Unit 5 · Tier 3	1/5	1%
DAC specifications & errors · Unit 5 · Tier 3	1/5	0.6%

3.Paper pattern (2025-26)

Section	Questions	Rule
A	7 × 2 marks	Attempt all
B	5 × 7 marks	Attempt any 3
C	11 × 7 marks	Attempt any 1

4.In the syllabus, never asked yet

Low priority, but read them once — a new paper can always start here.

ADC principle & specifications · U5

5.Study order

1Flip-flops (SR, JK, D, T) (Unit 3, Tier 1)
2K-map & tabulation method (Unit 1, Tier 1)
3Multiplexers (Unit 2, Tier 1)
4CMOS logic family (Unit 4, Tier 1)
5Adders & subtractors (Unit 2, Tier 1)
6Clocked sequential circuits (Unit 3, Tier 1)
7Binary codes & conversion (Unit 1, Tier 1)
8Boolean algebra & logic gates (Unit 1, Tier 1)
9Counters (Unit 3, Tier 2)
10Memories (RAM, ROM) (Unit 4, Tier 2)
11Logic family comparison (Unit 4, Tier 2)
12PLA, PAL & FPGA (Unit 4, Tier 2)
13R-2R ladder DAC (Unit 5, Tier 2)
14Shift registers (Unit 3, Tier 2)
15SOP, POS & canonical forms (Unit 1, Tier 2)
16Number systems & arithmetic (Unit 1, Tier 2)

FAQ

Which units of BEE401 carry the most marks?

Unit 3 (Sequential logic design, 25% of past marks) and Unit 1 (, 25% of past marks).

Do AKTU Digital Electronics questions repeat?

Yes. On average 50% of the marks in each newer BEE401 paper came from questions already asked in an earlier paper, and 26 questions have appeared in more than one paper.

How is this list made?

Every question from the 5 papers (2021-22–2025-26) was mapped to the current AKTU syllabus and grouped with the same question from other years. Questions are ranked by how many papers they appeared in, then by how recently.

Study this subject

Note: this is based on past AKTU papers, not a guarantee. Questions are mapped to the current syllabus; topics that are no longer in the syllabus are left out.