Computer Organization And Architecture (BCS302) - AKTU Question Paper 2023-24
B.Tech · Semester 3 · Free PDF Download
This is the official AKTU Computer Organization And Architecture Previous Year Question Paper for B.Tech Semester 3, academic session 2023-24. Published by Dr. A.P.J. Abdul Kalam Technical University (AKTU/UPTU), Lucknow. Free PDF download — no login required.
Course:B.Tech
Semester:Semester 3
Session:2023-24
University:AKTU / UPTU
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Questions Asked in 2023-24
Computer Organization And Architecture (BCS302) — extracted question text · 70 marks · 3 Hours
Section AAttempt all q u e s t i o n s i n b r i e f .
- aWhat are the different types of Buses used in computer architecture? 2
- bName the different types of multipliers. 2
- cWhat are the different phases of an instruction cycle? 2
- dHow does control unit of a computer works? 2
- eWrite a short not on locality of reference. 2
- fDefine 2 ½ D memory organization. 2
- gIn what way synchronous and async hronous serial modes of data transfer differ? 2
Section BAttempt any three o f t h e f o l l o w i n g :
- aWhat is meant by the term BUS arbitration? Why is it needed? How can bus arbitration be implemented in Daisy changing scheme?
- bShow the multiplication proces s using Booth’s algorithm when the following numbers are multiplied
- cWhat is pipelining? What are the different stages of pipelining? Explain in detail. 7
- dGive classification of memory based on the method of access. Also discuss construction and working of magnetic disk and various components of disk access time
- eWhat are the basic difference s between interrupt initiated I / O a n d p r o g r a m m e d I/O? Explain in detail
Section CAttempt any one p a r t o f t h e f o l l o w i n g : 7 x 1 = 7
- aWhat do you mean by processor organization? Explain various types of processor organization with suitable example
- bDifferentiate between Memor y stack and register stack. 7
- aExplain in detail the principle of carry looks ahead adder a nd design 4-bit CLA adder
- bRepresent the following decimal number in IEEE standard floa ting-point format in
- asingle precision method (32 bit) representation method
- aExplain the different cycles of an instruction execution. 7
- bDifferentiate between hardwir ed and micro programmed control unit. Explain each component of hardwired control unit organization
- aConsider a cache (M1) and memory (M2) hierarchy with followi ng characteristics: M1 : 16K word, 50 ns Access time M2 : 1M word, 400 ns Access time Assume 8-word cache blocks and set size 256 words with set associative mapping. (i) Show and explain the mapping between M2 and M1. (ii) Calculate the effective memor y access time with cache hit ratio=0.95
- bExplain the direct mapping t echnique. Consider a digital com puter has a memory unit of 64k*16 and cache memory of 1k words. The cache uses direct mapping with 4 block size of four words. (i) How many bits are there in the tag, block and word fields of the address format? (ii) How many blocks can the cache accommodate?
- aWhat do you mean by asynchronou s data transfer? Explain stro be control and handshaking mechanism
- bExplain the various modes of data transfer and discuss direc t memory access mode in detail. Also explain how DMA is superior to other modes
Question text is extracted from the official AKTU question paper PDF above. Check the original PDF for equations, diagrams and complete wording. Extracted: 2026-08-23.
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